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Resume of NLF
Lead Consultant
EXPERTISE AND SERVICES
Product Engineer, Product Technology Manager, Semiconductor Engineering Consultant, Process Architect, Device Engineer, Test Engineer, Wafer Fabricator Consultant, Engineering Failure Analysis, Accident Investigation, Accident Reconstruction, Specialist, Forensic Investigator, Product Liability, Expert Witness Testimony, Patent Infringement, Expert Witness Testimony, Engineering Consulting ServicesExpertise in electronics, semiconductor industry, transistor design, chip industry, product development, silicon verification, foundry selection and management, final test and assembly programs, failure analysis, and reliability testing. Highly experienced in areas including final test and assembly programs, first-rev silicon, wafer fabricators, expert witness testimony, and patent infringement litigation.
This associate offers specific expertise relative to semiconductor product investments, quality control, yield enhancement, yield improvement, data mining software, wafer fabs, tool development, account management, customer relations, and sales support.
Specialization includes DRAM, SRAM and NVM, microprocessor, mixed-signal, analog, discrete RF and power, process architecture, device engineering, test engineering, test maintenance, test manufacturing, 200mm DRAM wafer fab startup, and 350nm 64M DRAM process set up, BiCMOS and CMOS mixed-signal, CMOS logic with embedded SRAM, and NVM technologies.
Expertise includes technology transfer, product qualification, yield, performance, quality metric ownership, process integration, device engineering, circuit, process and device modeling, and DFM. Additional experience and specialization includes submicron class-1 production fab startup, unit process development, parametric test, SPC, yield modeling, CFM, SPICE modeling, device characterization, design rule optimization, circuit design, RISC-based microprocessor products, device test, wafer fab startup, fab production problems, quality failure issues, yield issues, and process improvement.
Additional areas of interest include bipolar processes, dual-poly-emitter bipolar devices, Intel processor, wafer sort, laser, design rule limitations, defect arrays, HCE testing, transistor and interconnect reliability, SUPREM, SEDAN, Minimos, Composite Schottky Design Rules, ECL design rules for gate array projects, diode arrays, bit slice microprocessors and PALs, device design, bipolar PROM's, and bipolar product engineering
PRINCIPAL INDUSTRIES SERVED
Consumer Electronics, Computers, Microchip, Semiconductor
EDUCATION
M.S.E.E., President’s Fellow, The Georgia Institute of Technology
B.S.E., Magna cum Laude, Phi Beta Kappa, University of South Carolina
PROFESSIONAL EXPERIENCE
Lead Consultant, Kevin Kennedy & Associates, Inc.
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Providing product engineering consulting, semiconductor engineering consulting, product technology management, process architecture, device engineering, test engineering, wafer fabricator consulting, failure analysis, forensic engineering and related expertise to a wide variety of clients.
Speak to this experienced, world-class expert now.
- Call (317) 536-7024
- E-mail nlf@rapid-response-consulting.com
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Or, peruse our 325 case studies or 475 other expert resumes.
Consulting Services Manager, Applied Materials, Austin, TX
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Joined Applied through the acquisition of GKS. Was responsible for the delivery of consulting services for the Yield Enhancement Services group, proprietary data mining and analysis software used to identify and resolve yield, control and quality problems relating to products produced in the customers’ wafer fabs.
Consulting Services Director, Global Knowledge Services, Austin, TX
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One of the founding partners of a new startup selling technology consulting services to wafer fab customers, hired and managed the consulting staff and developed the service offerings, supported tool development, account management, customer relations, and sales support, performed analysis of customer data for yield improvement services. Fortune 500 customers ranged from contact-print discrete lines to 130nm copper CMOS technology. Company acquired by Applied Materials.
Director of Product Technology, Samsung Austin Semiconductor, Austin, TX
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Responsible for Product Engineering, Process Architecture (integration), Device Engineering, Test Engineering, Test Maintenance and Test Manufacturing. Assisted in building all of these groups from scratch as an early management hiree.
State-of-the-art 200mm DRAM wafer fab startup, initial process set up for a 350nm 64M DRAM process. Led organization through four generations of technology and to best-in-the-world yields and AQL’s on a 230nm 128M process. My division had primary responsibility for the technology transfer, process setup and product qualification including yield, performance, and quality metric ownership.
Also served as Chairman of the Process Change Control Board that drove the setup of the initial spec systems and approved all initial specs, controlled all process changes, test changes, and any technical spec change and all experimentation. Served on the HR, Policy, Patent and Philanthropy committees.
Sr. Manager of Technology Development, Computer and Communications Group, National Semiconductor Corp., Arlington, TX
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Built new development group created by a strategic change to a distributed development model. Staffed, organized and directed organization to support a two-fab facility with process technologies including BiCMOS and CMOS mixed-signal, along with CMOS logic with embedded SRAM, and NVM technologies to 0.5um with advanced device structures and multilevel interconnects, including Process Integration, Device Engineering, Circuit, Process and Device modeling, DFM, and Unit Process development activities. Also managed the transfer of technology into our fabs and out of our fabs to other National fabs.
Engineering Manager, Computer and Communication Group, National Semiconductor Corp., Arlington, TX
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Responsible for engineering activities in a startup submicron class-1 production fab, including Device Engineering, parametric test, SPC, yield modeling, yield enhancement, and CFM. Delivered an ahead-of-schedule fab startup with full device, process and fab qualification on first runs as well as yield on the first lot, wafer and die tested.
Principal Device Scientist, RISC Microprocessor Design, Semiconductor Products Sector, Motorola, Austin, TX
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SPICE modeling and device characterization, design rule optimization, and the integration of the process development and circuit design efforts in support of the development of advanced RISC-based microprocessor products. Led the design of the process development and modeling test chips. Also served as the Principal Device Engineer for the Power PC transfer and completed the generation of the initial SPICE model files used by Motorola, IBM, and Somerset.
Principal Staff Engineer, DRAM Technology Dept., Semiconductor Products Sector, MOS Memory Products Division, Motorola, Austin, TX
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Responsible for the Device Engineering activities to support the transfer of Toshiba 1M and 4M DRAM technology into production in Motorola and joint venture wafer fabs. Analyzed wafers, product and data from all fabs and compared the performance of the fabs to ensure that the process was matched and that the product was consistent from all wafer fabs, including modeling, parametric test, failure-analysis, and process characterization. Also supported other Motorola product and development groups with modeling, and device test and characterization. Provided engineering support for fab startup and production problems at all facilities including qual fail issues, yield issues and process improvements.
Principal Device Engineer, Bipolar Technology Development, Advanced Micro Devices, San Antonio, TX
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Process and Device modeling and simulation in support of the development of advanced Bipolar processes. Developed models for dual-poly-emitter Bipolar devices from process definition through SPICE model decks, resulting in circuit performance modeling to within 10% of the initial Silicon, and continued this function through the technology exchange joint venture with Sony Corporation who subsequently bought the venture.
Process Development Engineering Manager, Fab X, Advanced Micro Devices, Austin, TX
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Head of the engineering department responsible for the Device Engineering, Process Integration and yield enhancement functions. Developed new process technologies including the 64K DRAM, nMOS SRAM and a triple-poly (1.0 um) 16K FSRAM.
My group created and brought into production the process to produce the second-source Intel 80186 and 80286 processor families with superior performance, costs and yields versus the Intel process. Accountable for wafer sort, laser, parametric test, and yields in a then state-of-the-art 5" MOS wafer fab.
ADDITIONAL EXPERIENCE
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Device Engineering Supervisor, Modeling Department, Mostek Process R&D, Carrollton, TX
Lead the group that was responsible for the characterization of process experiments in support of the development of 64K, 256K and 1Mbit DRAM process technologies.
I was one of the principal contributors to the development of the process test vehicles and directed the layout of those designs. Designed the process verification structures, the test structures for the verification of design rule limitations, and defect arrays. One of the primary authors of the Design Rule Manual and the principal author of the Layout Design Rules and the modeling decks. Directed efforts toward HCE testing and transistor and interconnect reliability screening for process R&D. Supported Process R&D with modeling using SUPREM, SEDAN, Minimos and other tools. Developed the circuit models for the 64K cell/bitline structures and improved Mostek's proprietary SPICE model equations.
Bipolar Product Engineering Manager, Semiconductor Division, Data General Corp., Sunnyvale, CA
Responsible for process integration, device engineering, parametric testing, and new product introduction for bipolar product lines of >150 products. Process technologies ranged from diode arrays to bit-slice microprocessors and PALs. We produced every chip in the Nova and Eclipse computers. Author of the Composite Schottky Design Rules used for PALs, PROMs and uP's as well as the ECL design rules for gate array projects. Designed the process development test vehicles and supported the process development efforts for all processes.
Product Engineer, Monolithic Memories, Inc., Sunnyvale, CA
Responsible for the 8M family of Bipolar PROM's, PAL's, and the introduction of a new line of interface chips. Also helped debug and fix several process problems in support of the startup of a new 4” wafer fab.
Semiconductor device and product engineer, expertise on device or transistor design, product and process development, yield enhancement and process improvement. Assist product development projects (chip industry), with model validation, silicon verification and foundry selection and management. Manage failure analysis, reliability testing, and final test and assembly programs. Ensure success of first-rev silicon, provide support for redesign success. Provide project planning and management, and full business plan development consulting for startup or critical projects. Consultant to wafer fabricators for yield enhancement, problem solving, and process and operational improvement. Expert witness testimony, and patent infringement litigation, including analyses, opinions and testimony. Investment advisors for semiconductor products, processes, and wafer fab and equipment issues, technologies, needs and trends.
Multi-national technology exchanges with Japanese, Korean, UK, and Israeli operations, with consulting experience with operations in the US, Mexico, Japan, China, Taiwan, Singapore, France, and Italy
Participated in nine wafer fab startups at every level from NCG to Director of Engineering
Product lines include DRAM, SRAM and NVM, Microprocessor, Mixed-signal, Analog, Discrete RF and Power
Please note that this is an abbreviated CV. A fully detailed unabridged CV is available under special circumstances.
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| Product Engineer, Product Technology Manager, Semiconductor Engineering Consultant, Process Architect, Device Engineer, Test Engineer, Wafer Fabricator Consultant, Engineering Failure Analysis, Accident Investigation, Accident Reconstruction, Specialist, Forensic Investigator, Product Liability, Expert Witness Testimony, Patent Infringement, Expert Witness Testimony, Engineering Consulting Services | |
| Resume of JMG | mechanical engineer, engineering manager, product design and documentation, engineering consultant, fatigue failure analysis, accident investigation, accident reconstruction, specialist, forensic analysis, investigation, product liability, expert witness testimony, |
| Resume of QFC | structural engineer, civil engineer, engineering consultant, engineering failure analysis, accident investigation, accident reconstruction, specialist, forensic investigation, expert witness testimony, engineering consulting services |
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Kevin Kennedy & Associates, Inc.
Rapid Response Engineering® Solutions
3905 Vincennes Road, Suite 320
Indianapolis, Indiana 46268
(317) 536-7000 voice
(317) 536-7220 fax