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Resume of JVX, Ph.D.
Consultant
EXPERTISE AND SERVICES
System-On-Chip (SOC) Testing, Integrated Circuit Expert ConsultantExpertise in integrated circuit testing, design for testability, and microfluidic biochips, real-time embedded systems and wireless sensor networks.
Areas of research interest include computer-aided design and testing of VLSI systems, design automation and testing of microfluidics-based biochips, cooling and thermal management of integrated circuits using droplet-based microfluidics, wireless sensor networks, ad hoc vehicular networks, delay-tolerant networking, and real-time embedded systems.
This consultant pioneered research on the testing and design for-testability of core-based system-on-chip (SOC) integrated circuits, and has been a leading influence worldwide in the emergence of this research area. This consultant was the first to define the problem of SOC test planning, developing the earliest optimization techniques and mathematical models for SOC test automation. This consultant is the author/co-author of the first published papers on SOC test scheduling, wrapper design and optimization, and test access mechanism optimization. With a collaborator at Philips Research Labs, this consultant developed a set of benchmark SOCs that have been widely used in the research community. This consultant has led the field with innovations in test planning for hierarchical SOCs, testing of mixed-signal SOCs, the use of virtual test access mechanisms, thermal-aware test scheduling, wafer-level testing of core-based SOCs, and interconnect/signal integrity testing for core-based SOCs.
Other noteworthy areas of expertise include test data compression for integrated circuits, with work based on compression codes, such as the Golomb code, the FDR code, the alternating run-length codes, dictionary-based compression, built-in self-test, and test response compaction.
This consultant is an expert in design automation for microfluidics-based biochips, being the first to relate microfluidic biochips to electronic design automation. Recognized as a pioneer in this area with publications and tutorial papers on synthesis, simulation, and testing. This consultant is a frequent IEEE Distinguished Speaker on system design issues related to biochips, and has delivered numerous keynote and invited talks at conferences.
As an expert in embedded real-time systems, this consultant developed the first unified framework for dynamic power management and run-time fault tolerance. Pioneered research on device scheduling for dynamic power management in hard real-time systems. Authored influential paper on network flow techniques for dynamic voltage scaling in hard real-time systems.
Specializing in wireless sensor networks, this consultant made fundamental contributions to algorithms for sensor node deployment, coverage enhancement, and network self-organization.
With collaborators, this consultant developed the theory of identifying codes on graphs, which has been studied extensively since then in the Information Theory community
PRINCIPAL INDUSTRIES SERVED
Computer Science, Electrical and Computer Engineering, Research
EDUCATION
Ph.D., Computer Science and Engineering, University of Michigan, Ann Arbor, MI
M.S.E., Computer Science and Engineering, University of Michigan, Ann Arbor, MI
B.Tech, Computer Science and Engineering, Indian Institute of Technology, Kharagpur, India
PROFESSIONAL EXPERIENCE
Consultant, Kevin Kennedy & Associates, Inc.
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Providing expertise in computer science and engineering, system-on-chip (SOC) testing, integrated circuit testing, design for testability, and microfluidic biochips, real-time embedded systems, wireless sensor networks, and related expertise to a wide variety of clients.
Speak to this experienced, world-class expert now.
- Call (317) 735-4804
- E-mail jvx@rapid-response-consulting.com
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Professor, Department of Electrical and Computer Engineering, major university
Associate Professor, Department of Electrical and Computer Engineering, Duke University, Durham, NC
Visiting Professor (Humboldt Research Fellowship), Institute for Computer Science, University of Potsdam, Germany
Visiting Professor, Kyushu Institute of Technology, Iizuka, Japan
Humboldt Research Fellow and Visiting Professor, Institute for Computer Science, University of Potsdam, Germany
Assistant Professor, Department of Electrical and Computer Engineering, Duke University, Durham, NC
Mercator Visiting Professor (supported by Deutsche Forschungsgemeinschaft), Institute for Computer Science, University of Potsdam, Germany
Guest Researcher, Institute for Computer Science, University of Potsdam, Potsdam, Germany
Assistant Professor, Department of Electrical and Computer Engineering, Boston University, Boston, MA
ADDITIONAL EXPERIENCE
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raduate Research Assistant, Advanced Computer Architecture Laboratory, Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI
Consulting Positions
Consultant, Johnstech International Corporation, Minneapolis, MN
Consultant, Spectrum Sciences & Software, Fort Walton Beach, FL
Technology Evaluation Consultant, Advanced Technology Ventures, Waltham, MA
HONORS AND AWARDS
Fellow of IEEE
Associate Editor Outstanding Performance Award (Certificate of Appreciation), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Circuits and Systems Society
Prof. Arun Kumar Choudhury Best Paper Award, IEEE International Conference on VLSI Design, Bangalore, India
ACM Senior Member
Distinguished Lecturer, IEEE Circuits and Systems Society
Distinguished Visitor, IEEE Computer Society
Best Paper Award, IEEE International Conference on Computer Design, San Jose, CA
Humboldt Research Fellowship, awarded by the Alexander von Humboldt Foundation, Germany
Nominated for Best Paper Award, IEEE/ACM Design Automation Conference
Nominated for Best Paper Award, IEEE Transactions on CAD/ICAS
Best Paper Award, IEEE Design Automation and Test in Europe (DATE) Conference, Munich, Germany
Office of Naval Research Young Investigator Award
IEEE Senior Member
Co-author of paper that received TTTC Jamses Beausang Best Student Paper Award at the IEEE VLSI Test Symposium, Montreal
Mercator Professor Award, Deutsche Forschungsgemeinschaft (German Federal funding agency), Germany
National Science Foundation Early Faculty (CAREER) Award
Nominated for Distinguished Dissertation Award, University of Michigan
PROFESSIONAL AFFILIATIONS
Fellow, IEEE
Senior Member, ACM
Member, Sigma Xi
PUBLICATIONS
Holds and has applied for patents in areas including circuit with built-in self test, self-organizing sensor node system, cross-referencing-based droplet manipulation method for high-throughput and pin-constrained digital microfluidic arrays, broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips, and droplet-trace-based array partitioning and a pin assignment algorithm.
Author of numerous books, book chapters, tutorials, journal publications, refereed conference publications, workshop presentations, and invited conference talks on topics related to and including microelectrofluidic systems: modeling and simulation, test resource partitioning for system-on-a-chip, SOC (system-on-a-chip) testing for plug and play test automation, scalable infrastructure for distributed sensor networks, design automation methods and tools for microfluidics-based biochips, digital microfluidic biochips: synthesis, testing, and reconfiguration techniques, and adaptive cooling of integrated circuits using digital microfluidics, fault isolation and diagnosis in multiprocessor systems with point-to-point connections, adaptive checkpointing with dynamic voltage scaling in embedded real-time systems, dynamic power management in wireless sensor networks, operating system power management, coverage-driven sensor deployment, a hierarchical design platform for microelectrofluidic systems (MEFS), advances in target tracking and active surveillance using wireless sensor networks, a scalable self-configuration and adaptive reconfiguration scheme for dense sensor networks, modular testing and built-in self-test of embedded cores in system-on-chip integrated circuits, efficient modular testing and test resource partitioning for core-based SOCs, microfluidics-based biochips: technology issues, implementation platforms, and design automation challenges, and more.
Please note that this is an abbreviated CV. A fully detailed unabridged CV is available under special circumstances.
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Kevin Kennedy & Associates, Inc.
Rapid Response Engineering® Solutions
3905 Vincennes Road, Suite 320
Indianapolis, Indiana 46268
(317) 536-7000 voice
(317) 536-7220 fax